The present invention relates to a semiconductor memory device, and more particularly relates to improving the reliability of a semiconductor memory device.
In recent years, as the digital technology is further developed, the performance of electronic units has been enhanced in order to process an even greater amount of data at a time. For that purpose, the number of semiconductor devices integrated on a chip for use in any electronic unit is rapidly increasing.
In a DRAM, a silicon dioxide film or a silicon nitride film has been used as a capacitive insulating film for a memory cell capacitor. However, to further increase the number of DRAMs integrated on a chip, a technique of using a high-dielectric-constant film as a capacitive insulating film for a memory cell capacitor has been widely researched and developed. Furthermore, to implement a nonvolatile RAM capable of performing high-speed write and read operations at a low voltage applied, a technique of using a ferroelectric film, exhibiting spontaneous polarization, as a capacitive insulating film for a memory cell capacitor has been vigorously researched and developed.
A planar memory cell has been used for a known semiconductor memory device. However, for a semiconductor memory device in which a high-dielectric-constant or ferroelectric film is formed as a capacitive insulating film for a memory cell capacitor, a stacked memory cell is used in order to realize a densely integrated memory operating at high speeds on the order of megabits.
Hereinafter, a known semiconductor memory device will be described with reference to the drawings.
FIG. 7 is a cross-sectional view illustrating a memory cell 100 for a semiconductor memory device disclosed in Japanese Laid-Open Publication No. 11-3977. As shown in FIG. 7, the memory cell 100 is implemented by integrating an MIS transistor 101 and a memory cell capacitor 102 together on a substrate. Source and drain regions 103a and 103b and a gate electrode 104 are formed around a semiconductor substrate, thus making up the MIS transistor '101. Further, a passivation film 105 is formed over the substrate. The memory cell capacitor 102 includes lower and upper electrodes 106 and 108 and a ferroelectric film 107 interposed between the electrodes 106 and 108. The lower electrode 106 is made up of Ti film 106a, oxygen barrier film 106b and Pt film (not shown) that are stacked in this order. The MIS transistor 101 and memory cell capacitor 102 are connected together via a contact plug 109 that passes through the passivation film 105 to reach the drain region 103b and to make electrical contact with the lower electrode 106.
However, in the known memory device, the contact plug 109 cannot make good contact with the lower electrode 106 in the memory cell capacitor 102.